1. Field
This patent document relates to a semiconductor design technology, and more particularly, to a column control signal generation circuit of a semiconductor memory device, which generates an input/output strobe signal.
2. Description of the Related Art
A semiconductor memory device performs a write operation of storing data and a read operation of reading stored data. During the write operation, the semiconductor memory device transmits data loaded in a global input/output line (GIO) to a local input/output line (LIO) through a write driver when a corresponding word line (WL) is enabled by an active signal. Then, the semiconductor memory device transmits the data loaded in the local input/output line to an input/output sense amplification unit which is selected by a column select signal, and stores the data in a target memory cell. On the other hand, during the read operation, the semiconductor memory device amplifies data stored in a target memory cell through a bit line (BL) using the input/output sensing amplification unit, when a corresponding word line is enabled by an active signal. Then, the semiconductor memory device transmits the amplified data to the local input/output line using a column select signal, and the data is amplified through the input/output sense amplification unit. The input/output sense amplification unit transmits the data loaded in the local input/output line to the global input/output line in response to an input/output strobe signal. Then, the semiconductor memory device activates the input/output strobe signal when the data of the local input/output line is properly amplified, that is, when the local input/output line secures a voltage level difference ΔV for the data.
However, due to a change in delay amount which may be caused by a variety of process, voltage, and temperature variations, the conventional semiconductor memory device may activate the input/output strobe signal when a sufficient voltage level difference ΔV of the local input/output line is not secured. In this case, the reliability of the read operation of the semiconductor memory device may be degraded.